1. Field of the Invention
The present invention relates to an insulated gate type semiconductor device, and a method of manufacturing the same. In particular, the present invention relates to the structure of a power semiconductor element having a trench gate, and to a method of manufacturing the same.
2. Description of the Related Art
One type of power insulated-gate bipolar transistor (power IGBT), that is, a trench IGBT, is configured in a manner that trench IGBT cells having the trench gate structure are provided in parallel on a semiconductor substrate. Each trench IGBT cell has the trench gate structure using the trench sidewall of a MOS gate buried in a trench as a channel region. In the trench IGBT as described above, channel resistance is reduced, and low loss is facilitated.
JPN. PAT. APPLN. KOKAI Publication No. 10-163483 by the same assignee as the present application discloses the following advanced injection enhanced gate transistor (IEGT). The IEGT uses the trench gate structure and carrier storage effect on the emitter side. The entire contents of the reference are incorporated herein by reference.
FIG. 1 is a cross-sectional view schematically showing the structure of the IEGT disclosed in the reference. FIG. 2 is an enlarged sectional view showing part of the IEGT shown in FIG. 1.
In the IEGT shown in FIG. 1 and FIG. 2, a P− base layer 107 is formed on the surface of an N− base layer 101 having high resistance. Several P+ base layers 107a are selectively formed on the surface region of the P− base layer 107 along the horizontal direction at constant pitch. Several trenches are selectively formed at constant pitch having the depth ranging from the surface of the P− base layer 107 to the N− base layer 101. A trench gate electrode 106 is buried in each trench via a gate insulator 105.
An N+ emitter layer 108 having high impurity concentration is selectively formed to contact with the side of the adjacent trench. In this case, the N+ emitter layer 108 is formed in the surface region of the P+ base layer 107a selected at intervals of the constant number of P+ base layers 107a and in the surface region of the P− base layer 107 adjacent thereto. The N+ emitter layer 108 is not formed in the surface region of the remaining P+ base layers 107a, which are not selected, and the surface region of the P− base layer 107 adjacent thereto.
An emitter electrode 109 is provided on the N+ emitter layer 108 and the P+ base layer 107a contacting therewith to contact with both of the former and the latter. The emitter electrode 109 short-circuits the N+ emitter layer 108 and the P+ base layer 107a. 
An interlayer dielectric 111 is provided to electrically isolate the emitter electrode 109 from P+ and P− base layers 107a and 107, which are not formed with the trench gate electrode 106 and the N+ emitter layer 108. Each trench gate electrode 106 is drawn out to a gate pad 116 via a polysilicon gate interconnect (wiring) pattern 115. The interlayer dielectric 111 electrically isolates the gate pad 116 and the emitter electrode 109.
On the other hand, the back side of the N− base layer 101 is formed with a P+ collector layer 103 having a high impurity concentration via an N+ buffer layer 102 having high impurity concentration. A collector electrode 110 is provided on the P+ collector layer 103.
In FIG. 1, reference numerals 16, 13, 14 and 117 denote guard ring, field plate, N+ filed stopper layer, and passivation insulator, respectively.
In the structure described above, the N− base layer 101, P− base layer 107, N+ emitter layer 108, gate insulator 105 and trench gate electrode 106 constitute a MOSFET. In the MOSFET, electrons are injected from the N+ emitter layer 108 to the N− base layer 101 through a channel region formed in the surface region contacting with the trench of the P− base layer 107.
The operation of the IEGT shown in FIG. 1 and FIG. 2 will be briefly described.
In order to turn on the IEGT, a predetermined positive gate voltage is applied between the trench gate electrode 106 and the emitter electrode 109. In this case, the gate voltage is applied in a state that a positive collector voltage is applied between the collector and emitter electrodes 110 and 109. By doing so, the surface region contacting with the gate insulator 105 of the P− base layer 107 is inverted to n type, so that an inverted channel can be formed. Thus, electrons are injected from the emitter electrode 109 to the N− base layer 101 through the inverted channel, and thereafter, reach the p-type collector 103. In this case, the junction between the p-type collector 103 and the N− base layer 101 is forward-biased via the N+ buffer layer 102. In addition, holes are injected from the p-type collector 103 to the N− base layer 101 via the N+ buffer layer 102. As described above, both electrons and holes are injected to the N− base layer 101. As a result, conductivity modulation occurs in the N− base layer 101, so that the resistance of the N− base layer 101 can be greatly reduced.
In the operation, carriers are stored to the portion formed with no N+ emitter layer 108 of P− base layers 107 held between adjacent trenches, that is, under a dummy base region. Thus, conductivity modulation effect is enhanced, so that on resistance can be reduced and the maximum cutoff current density can be made high.
On the other hand, in order to turn off the IEGT, a negative voltage to the emitter electrode 109 or voltage equal to (voltage applied to the emitter electrode 109) is applied to the trench gate electrode 106. By doing so, the inverted channel is lost; therefore, electron injection stops. With the stoppage of electron injection, injection of holes to the P− base layers 107 stops, and the resistance of the N− base layer 101 becomes high; therefore, the IEGT turns off.
However, the IEGT having the structure described above has the following problem when turning on. That is, the gate voltage oscillates by the effect of capacitance generated between carriers stored under the dummy base region and the trench gate electrode 106, and steps up more than the necessary. For this reason, the switching speed (dV/dt) becomes abnormally high; as a result, there is a possibility that the element is broken down.
FIG. 3 is a waveform diagram showing one example of oscillation of gate voltage (VGE) generated by carriers stored near the gate in the IEGT shown in FIG. 1 and FIG. 2. In FIG. 3, IC is a collector current, and VCE is a voltage between collector and emitter.
In general, the switching speed (dV/dt) control of the IGBT is carried out by controlling the gate current in accordance with the value of the gate resistor connected outside. However, in the IEGT having the structure shown in FIG. 1 and FIG. 2, the gate voltage changes by storage carriers. For this reason, it is difficult to control the gate current by the external gate resistor.
As described above, the conventional IEGT has the following problem. Carriers are stored near the gate, and thereby, when the IEGT turns on, the gate voltage oscillates, and steps up more than the necessary. For this reason, the switching speed (dV/dt) becomes abnormally high; as a result, there is a possibility that the element is broken down. Therefore, it is desired to solve the foregoing problem.